Blind Adaptive Signal Cancellation for Wide Dynamic Range A/D Converter

The very high-resolution V Corp analog-to-digital converter with Adaptive Signal Cancellation (ASC) uses a two or more stages of high-speed, high-resolution analog-to-digital converters (ADCs) with blind adaptive interstage matching to successively cancel large signals from the analog input and thereby allow very wide dynamic range digitization of the lower level signals. Conventional pipelined subranging ADC architectures without V Corp’s proprietary ASC signal processing suffer from transfer function discontinuities due to gain, phase, and DC-offset mismatches between the multiple ADCs. These discontinuities introduce nonlinear distortion that severely limits the usable Spurious Free Dynamic Range (SFDR). The ADCs must be matched extremely accurately to enable high-resolution performance, which is very difficult to accomplish because the mismatches are a function of input frequency, amplitude, sample rate, and even small temperature changes. The key to the efficacy of the Adaptive Signal Cancellation architecture is the ability for the processing to calibrate itself in the background to insure optimal dynamic range by cancelling large signals. This technology provides significantly higher dynamic range than state-of-the-art ADCs: approximately 36 dB improvement in dynamic range compared to current 8-bit and 10-bit 1.2 GSPS ADCs, and three times the bandwidth of current 12-bit, 400 MSPS ADCs. The extremely high spur free dynamic range that the architecture provides allows the accurate detection of very small signals in an environment with high-power interference which significantly reduces co-site inference issues. The architecture (including multiple ADCs, DACs, support electronics and adaptive processing) can be implemented in a compact, low-power custom ASIC or a printed-circuit board with discrete components and an FPGA. A 12-bit, 1.2 GSPS A/D converter can be realized in a compact package using currently-available commercial off-the-shelf parts. This represents “true” 12-bit dynamic range (i.e., SFDR > 85 dB), which allows the accurate detection of small signals in the presence of simultaneous very large level signals. It provides direct RF conversion up to 1.2 GHz. This approach can be customized for different bandwidth and dynamic range requirements by selecting different base ADC and DAC chips and/or using more stages of A/D conversion in the architecture and, as a core technology, is widely applicable to numerous projects. The ASC approach is also suitable for use with superconducting ADCs and DACs and provides a direct path to SFDR > 130 dB with direct RF conversion over several GHz of bandwidth. During Phase II, the architecture will be demonstrated using real-time hardware data. General Dynamics has committed to being a Phase II partner with V Corp on this project and, once successfully demonstrated, is very interested in being a Phase III transition partner.