Radiation-Hardened Memory

Silicon Space Technology (SST), working with Texas Instruments (TI), proposes to demonstrate the feasibility of building large (64Mb) SRAM’s for space applications by applying SST’s proprietary hardened-by-process (HBP) techniques to TI’s 90nm C027 process. SST’s HBP modules have solved the major space radiation problems, Single-Event Effects (SEE), Total Ionizing Dose (TID), and Dose Rate (DR). Sequences of radiation tests on various 180nm devices from multiple foundries have shown SST HBP modules significantly improve SEE performance (e.g., SEL, SET, SEU & MBU), DR and TID compared to non-HBP protected circuits. Furthermore, SST’s HBP modules do not adversely affect either circuit performance or yield. Our proven-in-silicon approach enables production of radiation-hardened integrated circuits at leading-edge circuit densities within any commercial silicon foundry. SST’s first product, a RH 16Mb SRAM designed and manufactured in TI’s 180nm C05 process, has now demonstrated good functionality, yield, and impressive radiation performance. SST is also currently developing a 130nm RH dual-port SRAM based on TI’s 130nm process. In addition to making large (64Mb) RH SRAM’s feasible, applying SST’s HBP methods to TI’s 90nm process will make it feasible to bring RH versions of TI’s existing and future portfolio of 90nm products to the marketplace.