The Characterization and Mitigation of Single Event Effects in Ultra-Deep Submicron (< 90nm) Microelectronics

Orora Design Technologies proposes to develop electronic design automation (EDA) tools employing minimally invasive circuit design-based methods to mitigate single event effects (SEEs) for next generation Ultra-DSM CMOS (<90nm) space electronics. Robust circuit modeling, simulation and optimization tools will be developed to allow circuit designers to quickly identify sensitive SEE circuitry, characterize the SEE sensitivity, and automatically insert the minimally invasive SEE mitigation into complex circuit designs, and then optimize the performance of an ultra-DSM circuit while meeting the radiation-hardness requirements with the minimal area and performance overhead. The SEE design-based mitigation EDA tool, as well as enabling modeling, simulation and optimization tools, will be integrated into industry standard design environments with automated design flows. The proposed tool development will be driven by, and validated against, several 90nm and below real circuits from a collaborative project with Boeing Solid-State Electronics Development for satellite systems.