The Characterization and Mitigation of Single Event Effects in Ultra-Deep Submicron (< 90nm) Microelectronics

Orora Design Technologies proposes the development of minimally invasive circuit design-based methods to mitigate single event effects (SEEs) in next generation Ultra-DSM CMOS (<90nm) circuits for space-based applications. Novel robust circuit modeling and simulation techniques will be developed and demonstrated which will allow circuit designers to quickly identify sensitive SEE circuitry, characterize the SEE sensitivity, and automatically insert the minimally invasive SEE mitigation into complex circuit designs, and then optimize the performance of an ultra-DSM circuit while meeting the radiation-hardness requirements with the minimal area and performance overhead. The SEE design-based mitigation methods, as well as enabling modeling, simulation and optimization techniques, will be implemented as electronic design automation (EDA) tools integrated into industry standard design environments with automated design flows. The proposed tool development will be driven by, and validated against, several 90nm and below real circuits from a collaborative project with Boeing Solid-State Electronics Development for satellite systems.