SEE Modeling and Mitigation in Ultra-Deep Submicron Microelectronics

As technology feature sizes decrease, single event upset (SEU), digital single event transient (DSET), and multiple bit upset (MBU) effects dominate the radiation response of microcircuits. Recent test circuits and test methods have quantified the pulse widths of DSETs generated from heavy-ion strikes on critical microcircuit nodes. These pulse widths have proven to be much larger than previously thought, which substantiates the importance of DSET induced errors to the soft error rate (SER) of modern microcircuits. In Phase II, we will extend our Phase I single event effect (SEE) circuit modeling approaches which couple the circuit response to the charge collection mechanisms. This new work will incorporate second order recombination and diffusion effects and enable efficient and cost effective SEE simulation of advanced microcircuits. New test structures and test circuits will be designed, fabricated, and characterized in order to evaluate emerging SEE mitigation approaches based on process modifications, design hardening techniques, and substrate engineering approaches.