SEE Modeling and Mitigation in Ultra-Deep Submicron Microelectronics

As technology feature sizes decrease, single event upset (SEU), digital single event transient (DSET), and multiple bit upset (MBU) effects dominate the radiation response of microcircuits. Recent test circuits and test methods have quantified the pulse widths of DSETs generated from heavy-ion strikes on critical microcircuit nodes. These pulse widths have proven to be much larger than previously thought, which substantiates the importance of DSET induced errors to the soft error rate (SER) of modern microcircuits. We apply new circuit SEE modeling approaches which couple the circuit response to the charge collection mechanisms. Our approach uses standard SPICE circuit elements, is easily calibrated, and runs as fast as conventional current injection simulations. This enables efficient and cost effective SEE simulation of advanced microcircuits. New mitigation approaches are proposed to improve the heavy-ion response of ultra-deep submicron integrated circuits. These approaches are minimally invasive to existing fabrication processes and can be transparently applied to existing bulk CMOS microcircuit layouts. The proposed methods include process modifications, design hardening techniques, and substrate engineering approaches.