Digital Antijam (AJ) Processing Application-Specific Integrated Circuits (ASIC) for Hand-held Global Positioning Satellite (GPS) Receiver

The Global Positioning System (GPS) is a critical element in numerous military and commercial applications. It is vital that GPS receivers operate efficiently in hostile jamming environments and in the presence of interference caused by multipath. A critical need is the development of an application specific integrated circuit (ASIC) which will enable incorporation of advanced anti-jam techniques such as Space Time Adaptive Processing (STAP) into handheld GPS receivers. RBS Technologies proposes to develop an Anti-jam (AJ) ASIC with robust STAP interference suppression techniques that is compatible with handheld GPS size and power constraints. STAP architectures were analyzed in the Phase I to identify potential low power candidates which are able to meet interference suppression and performance requirements. Also as part of the phase I, the power dissipation of key ASIC subsystems that are needed for an ASIC implementation of STAP (SFAP) was characterized and the key IC subsystems were integrated to develop preliminary system level VHDL designs for the selected AJ ASIC architecture. The Phase II effort will focus on refining the selected STAP architecture, developing and testing an FPGA prototype, and finally the developing and testing of 90 nm CMOS ASIC prototype.