Novel Mitigation Techniques for Reconfigurable Computers for Space Based Applications

Demand for high performance On-Board Processing (OBP) for space-based applications is being driven by the advancement of high speed sensors, downlink rates that are orders of magnitudes less than sensor data rates, and the desire for autonomous real-time operations. ReConfigurable Computers (RCC) based on Field Programmable Gate Arrays (FPGAs) are an excellent candidate for high performance processing, but they are susceptible to Single Event Upsets (SEUs). Traditional mitigation techniques such as triplication of code coupled with majority voting, designated as Triple Modular Redundancy (TMR), have proven effective in mitigating SEU effects for RCC systems. However, these methods come at a premium in Size, Weight, and Power (SWaP) and performance. For computationally-intensive systems with multiple gigabit data rates, these techniques while feasible might not be practical for the space environment where SWaP is a premium. To address the need for SEU mitigation while minimizing the impact to SWaP, novel mitigation techniques will need to be employed to fully capture the benefits of space based RCC processing systems.