Novel Mitigation Techniques for Reconfigurable Computers for Space Based Applications

FPGA-based reconfigurable systems'''' popularity for space-based applications has grown considerably due to their flexibility and the ability to multiplex in real time different hardware configurations.  A wider utilization of COTS FPGAs is limited by their susceptibility to Single Event Upsets (SEUs). A practical method to mitigate SEU upsets on FPGA-based systems will significantly impact the aerospace industry. This phase II project will implement and test a scrubbing solution designed at Micro-RDC during the phase I. The scrubber consists of an application specific microcontroller labeled Femto Controller. Femto is designed to support a limited set of instructions mainly dedicated to move data to and from the configuration memory (or any memory in general). Due to the programmability of Femto, the scrubber is flexible enough to support different Xilinx families as well as different configuration memory access ports. The prototype resulting from this phase will be implemented on Structured ASICs using  the Structured ASIC Rad Hard By Design (RHBD) IBM 9LP library and a design flow developed at Micro-RDC. This prototype, as well as the scrubber netlist for implementation on a programmable device will be at the core of the commercialization strategy for the next phase of this effort. BENEFITS: The scrubber has a direct impact on military and aerospace applications. Its success will allow designers to work with COTS with some level of reliability without having to incurring in the excessive cost of using radiation hardened devices. If successful this solution could be used in any digital system susceptible to SEUs with little or no modification. In particular, a Plug and Play variation of the scrubber solution provides support for legacy hardware at little cost.