Hybrid CMOS/Nanodevice Integrated Circuits

Ultra-dense integrated circuits with sub-10-nm features would provide enormous benefits for all information technologies, including computing, networking, and signal processing. However, it is widely accepted that a radical paradigm shift from purely CMOS technology to hybrid CMOS/nanodevice circuits is essential to achieve such level of miniaturization. We propose to work on a particular circuit concept, dubbed CMOL, for which the application prospects look best. Such a circuit would combine a level of advanced CMOS fabricated by the usual lithographic patterning, and a nanodevices which are formed (e.g., self-assembled) at each crosspoint of a "crossbar" array, consisting of two levels of nanowires fabricated by an advanced patterning technique, such as nanoimprint or EUV interference lithography which have good prospects for the half-pitch reduction to 3 nm or so within the next decade. The crucial element of hybrid design is the interface between CMOS and nanodevices. In the CMOL circuits the interface will provided by pins that are distributed all over the circuit area, on the top of the CMOS stack. Silicon-based technology necessary for fabrication of pins with nanometer-scale tips has been already developed in the context of field-emission arrays.