Radiation Hardening Designs and Techniques for Missile Defense (Process)

Silicon Space Technology (SST) has solved the major space radiation problems, Single-Event Effects and Total Ionizing Dose, by combining substrate engineering with layout design innovation. Working with Texas Instruments (TI) to enable radiation hardening of TI’s 130nm commercial CMOS process (C035), SST’s radiation-hardening (RH) process innovations, previously demonstrated at 180nm, will be scaled and integrated into this process. SST will perform this work by relying heavily on process and device finite-element (or TCAD) simulation. SST will first build the baseline process model to develop the integration approach for inserting the RH process modules into the C035 130nm process. The TCAD model will be calibrated to process measurements and to electrical characteristics of the C035 transistors provided by TI. Using the calibrated TCAD model as a baseline, the simulations will be varied to develop the new RH 130nm process and to quantify any process interactions, constraints or yield limiting factors, especially in the context of circuit ground rules, SPICE models and photolithographic imaging.