Radiation-Hardened By Process Technique Demonstrated in Advanced Commercial 130 nm CMOS using 1.89 um2 Bit Cell and 16MB SRAM

In 2000, the DOD’s Radiation Hardened Microelectronics Oversight Council (RHOC) recognized the ever-widening performance gap between the manufacturing capability of existing radiation-hardened integrated circuit (RHIC) producers and the future demands of military satellites and key terrestrial systems. The RHOC predicts system requirements of currently planned satellites will require RHIC technology with feature sizes at or below 180 nm by the end of 2005. Silicon Space Technology, recognizing this opportunity, proposes the “RH client process” which takes the best attributes of commercial silicon suppliers and adds distinct process modules – thereby transforming the commercial silicon process from radiation-soft to radiation-hard. We have already demonstrated integration of both PID and BGR in silicon with radiation testing soon to follow. The technology is not limited by feature scaling so we intend to move forward to 130 nm – allowing us to close the technology gap between DOD RHIC electronics and advanced commercial. Our products will not only feature leading-edge scaled transistors, but will achieve similar circuit packing density. We believe our model is the only candidate solution that has any chance of meeting these DOD goals: • High-performance radiation-hardened IC components • Commercial circuit densities • Advanced Lower Cost manufacturing