Ultra Compact, Low Power, NIR, Flash LADAR Receiver

The object of this effort is to design a miniature, low power, angle-angle-range, 3-D flash LADAR receiver that can be implemented using germanium-on-insulator/silicon-on-insulator (GOI/SOI) hybrid wafer stacks. The germanium layer of the wafer stack will be used for photodetection functions, so as to take advantage of its excellent photoabsorption in the visible and NIR, as well as its high carrier mobilities. Low-noise, high-bandwidth amplification and pulse detection circuits will be fabricated in the silicon layer of the wafer stack, using mature complementary metal-oxide-semiconductor (CMOS) technology. The proposed design is optimized to be both low power and radiation tolerance. The SOI architecture is inherently tolerant of radiation, as the small volumes of device material involved have a correspondingly smaller scattering cross section. Moreover, isolation of the thin device layer from the substrate means that CMOS receiver circuits fabricated on such a wafer will benefit from increased speed, reduced power consumption, and lower noise. Finally, as the proposed design can be manufactured using commercial CMOS foundry lines, no additional cost, development time, or quality control measures relative to a standard CMOS process will be incurred, once the hybrid wafers are procured. In Phase I, the proposed receiver will be designed, simulated, and optimized using TCAD tools. The design and simulation tasks will be complemented with a short-loop fabrication experiment in which critical receiver components will be fabricated from hybrid GOI/SOI wafer prototypes and characterized.