High Speed Readout for Focal-Plane Array

A focal-plane array module will be developed including a read-out integrated circuit bump-bonded to a compound semiconductor avalanche photodiode array, supporting 3D imaging for coherent and incoherent pulsed ladars with range resolution finer than 15 cm. The ROIC, already in its fourth generation of optimization, implements a switched-capacitor array at each pixel as a 256-element analog buffer, sampling beyond 1 GSPS with < 200 electrons/sample of noise. Time-shared, 12-bit A/D converters on the ROIC then feed digital data trains out of the module's low-cost package. Merging the ROIC with high-gain APD pixels eliminates the need for preamplifiers, reserving more chip real estate for the sampler buffers. The phase I module will be used to prove that the approach is low risk and promises headroom for further improvement to range resolution, dynamic range, pixel pitch, and pixel count. It will also refine the Phase II specifications for 60 um pixel pitch.