Universal Short FEC Codec

The goal of this SBIR is to advance the state-of-the-art in forward error correction (FEC) coding in the very short block length regime. Traditionally, FEC code design has been tightly coupled to the target decoding algorithm. We are taking a very different design approach in this SBIR. Rather than choosing a decoding algorithm that constrains the choice of code, we apply universal algorithms that offer near maximum likelihood (ML) decoding of any code. This leaves us free to explore code designs that maximize minimum distance – and hence ML decoding performance – regardless of their underlying algebraic structure. In the proposed Phase II effort, Caliola will develop and demonstrate a product that (i) identifies the best known binary linear code with a given block length n ? 512 and dimension k < n and (ii) autogenerates encoders and decoders for that code. Our decoders use a computationally efficient variant of order statistics decoding to provide near-ML decoding performance. Our product will autogenerate C++ codecs that leverage GPUs when available, as well as VHDL codecs for FPGAs. Caliola’s Universal Short FEC Codec product will provide a turnkey solution for any commercial or DoD customer that requires short block length FEC for use in software-defined radios that are built on top of ARM processors or FPGAs.