SBIR/STTR Research Award
A Novel High Resolution ADC Architecture for Ultra Low Noise Measurements
Award amount
$139,402Program and phase
SBIR · Phase IAward year
2025Award details
- Awarding agency
- Department of Defense
- Branch
- Navy
- Recipient company
- Akyor LLC
- Proposal award date
- 2025-06-18
- Contract end date
- 2025-12-15
- UEI
- ZL2GM88TRCN7
- Solicitation number
- 25.1
- Topic code
- N251-048
Research abstract
3D Fluxgate Magnetometers demand an ADC with the noise level below -110dB at the Sampling Rate above 6 KHz. This is equivalent of 22-bit effective bit-resolution at 6KHz SR. This is beyond the capability of the most commonly used high-resolution high-sampling-rate ADC architectures because of employing discrete-time signal sampling techniques in a closed-loop digital control system. Conventional techniques employ a Digital to Analog Converter (DAC), a comparator or low-resolution ADC, and a converging algorithm to digitally construct the signal. While the design is optimized for miniaturization and power, the closed-loop discrete-time signal sampling allows for injecting the high frequency components of the digital signals into the analog and power section. In addition, in each iterating loop of conventional ADCs, the architecture demands a DAC/Comparator signal level depend on the input signal level in the feedback mechanism. In frequency domain, that means injecting a wide spectrum varying high frequency components of noise on the analog and power lines which is extremely difficult to filter at the level of -110dB. Over-sampling techniques and digital filtering allow for improving the SNR, but not at the level required for the target SR of better than 6 KHz.ÝIn this project we propose a novel continuous-time multi-channel ADC structure in an open-loop configuration that avoids injection of digital sampling noises on the analog section. This architecture is based on a sine-wave reference signal generated by a DAC. In frequency domain, the only digital noise impacting the analog performance is due to the sampling rate of the DAC and its distortion. Because the pre-determined DAC signal is repeated over the time, the digital noise spectrum will not vary by the change in the input voltages. It simplifies the process to filter the digital noises out of the power net and analog lines. This is the main advantage of this architecture compared to the other techniques.Ý
Technology keywords
Not reported
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Verified by an exact topic code match. This is not a text-similarity match.
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