ANALOG CMOS NEURAL CIRCUITS FOR SPEECH RECOGNITION

In order to become a feasible human interface technology suitable for operational deployment, real-time speech recognition requires orders-of-magnitude improvement in processing capability and an affordable implementation. We are currently developing analog CMOS speech recognition chips combining integrated silicon cochleae and neural networks based on auditory system modeling. We have demonstrated a prototype version of our low-precision highly parallel analog neural network in the laboratory. Under NSF funding, we will continue to research and develop these massively parallelo custom integrated circuits that will perform recognition of speaker-independent connected speech, using integrated delay lines and analog computing networks. During this Phase I, we propose to investigate robust speech processing as an intuitive interface to relieve crew work load and enhance crew safety. We will develop the performance specifications required for a speech system to solve a real Air Force human factors problem. We will also capture representative speech data, experiment with recognition of the data, and prepare for the Phase II effort to deploy a full-scale prototype speech recognition system based on our custom integrated circuits. This effort serves to focus our advanced neural network research on an important real-world problem and may lead directly to inexpensive products with wide commercial applicability.