SBIR/STTR Research Award

A Low-Power, Dynamically Reconfigurable Scalable Array Processor (DRSAP) for Software-Defined Universal Terminals with Integrated RF

Award identifier dcad14cd6ff21901b81496f507789c9541c1aa18866130a68141c30780f5900fAwarding agency Department of Defense · Air Force

Award amount

$1,248,562

Program and phase

SBIR · Phase II – Direct to Phase II

Award year

2025

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Award details

Awarding agency
Department of Defense
Branch
Air Force
Recipient company
XCELERIUM INC
Proposal award date
2025-05-23
Contract end date
2026-05-26
UEI
SHZHYRGBJU85
Solicitation number
X25.5
Topic code
AFX255-DPCSO1

Research abstract

The development of multiband communication systems for the Air Force (AF) and other DoD Departments necessitates highly flexible and energy-efficient processing of wideband RF signals. Current RF system-on-chip (RFSoC) solutions, which combine high-speed analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) with FPGA fabrics, are limited by low compute density, high power consumption, and large size. Custom ASICs, while offering better performance, are inflexible and require significant development budgets and time.Xcelerium proposes a novel solution to address these limitations with its Dynamically Reconfigurable Scalable Array Processor (DRSAP) technology. This technology combines the flexibility of general-purpose processors with the cost and power advantages of custom hardware. The DRSAP architecture consists of interconnected Edge Processing Units (EPUs) that offer compute densities more than 100× higher than modern FPGA devices, with over 10× lower power consumption. This makes it ideal for creating advanced, multi-antenna MMW RF systems that employ complex waveforms.The proposed Universal Terminal chip, built with RF transceivers and mixed-signal subsystems combined with DRSAP technology, is designed to be scalable, resilient, and fault-tolerant. It supports arbitrary waveform generation, digital signal processing of received signals, and operation in L, S, and C bands. The chip integrates an RF transceiver, data converters, and processors for ultra-low power operation while offering maximum flexibility.Xcelerium's technology, initially designed for commercial wireless, automotive, and industrial applications, is also well-suited for Air Force, Navy, and Defense applications. The DRSAP-based Universal Terminal can support multi-waveform modems for 4G, 5G, and DoD-specific secure waveforms, as well as advanced agile waveforms for modern multi-antenna phased-array, massive-MIMO, and hybrid-MIMO systems. Additionally, it can implement radar, communications, and RF sensing workloads using a C-based design flow, offering significantly lower power consumption than conventional programmable solutions.The proposed development leverages Xcelerium's experience in high-volume software-defined radio solutions for 4G/5G cellular and wireless connectivity devices and emerging 6G applications. The DRSAP technology promises to deliver ASIC-like performance and power consumption with the ease of development of C-based workflows, making it a unique and innovative platform for Air Force applications.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

3 SBIR/STTR records share this UEI (2023–2025). Reported award amounts total $2,648,470. Reported amounts are not federal obligations.

Phases: Phase II – Direct to Phase II, Phase I

Agencies: Department of Defense, National Aeronautics and Space Administration

Agency intelligence

Department of Defense

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