A NOVEL LINEAR SYNAPSE DESIGN FOR ANALOG NEURAL NETWORKS

TO BUILD FAST INEXPENSIVE ARTIFICIAL NEURAL NETWORK HARDWARE, A HIGH-PERFORMANCE BUT COMPACT SYNAPSE CIRCUIT IS REQUIRED. DIGITAL IMPLEMENTATIONS REQUIRE LARGE SYNAPSE CIRCUITS. EXISTING ANALOG SYNAPSE DESIGNS ARE HIGHLY NON-LINEAR OR REQUIRE EXPENSIVE FABRICATION PROCESSES. OUR NEW LINEAR SYNAPSE CIRCUIT IS SMALL, ALLOWS FOR ON-CHIP LEARNING, AND USES STANDARD CMOS BULK TECHNOLOGY AND SO RESULTING NEURAL NETWORK CHIPS CAN BE FABRICATED INEXPENSIVELY BY MANY VENDORS. WE PROPOSE TO DEVELOP, SIMULATE, LAYOUT, AND FABRICATE OUR NEW LINEAR SYNAPSE CIRCUIT DURING PHASE I. WE EXPECT TO SHOW DENSITY IMPROVEMENTS OF MORE THAN 100 OVER EXISTING CIRCUIT DESIGNS. THIS PROPOSED RESEARCH APPLIES OUR EXPERIENCE IN ANALOG CIRCUITS AND NEURAL NETWORK CIRCUITS TOCREATE A MAJOR IMPROVEMENT IN FUNCTIONALITY OF ARTIFICIAL NEURAL NETWORK SYSTEMS.