A REAL-TIME HIGH DENSITY CCD ARCHITECTURE

WE PROPOSE TO DESIGN AND DEVELOP AN ARCHITECTURE FOR CCD READOUT THAT WILL ALLOW A SINGLE HIGH-DENSITY CCD SENSOR TO GENERATE REAL-TIME READOFF RATES OVER MULTIPLE PARALLEL OUTPUT PINS OR SLOWER READOFF RATES OVER A SMALLER NUMBER OF PINS (E.G. ONE). A SIMPLE MODIFICATION TO THE OUTPUT STRUCTURE WILL ALLOW A SINGLE CCD DESIGN TO SERVE MULTIPLE APPLICATIONS BY OPERATING IN DIFFERENT READOUT MODES CONTROLLED BY INPUTS TO THE CCD. DURING PHASE I WE WILL REFINE THE CONCEPT. WE WILL ANALYZE RELEVANT TECHNOLOGIES FOR PERFORMANCE, MANUFACTURABILITY, AND COST. OUR PHASE I EFFORT WILL INCLUDE THE DESIGN, MODELING, AND FABRICATION OF A SMALL CCD CHIP TO PROVE THE FEASIBILITY OF OUR DEVELOPMENT. OUR APPROACH WILL UTILIZE FABRICATION BY EITHER LORAL (FORD) AEROSPACE OR ORBIT SEMICONDUCTOR. ANTICIPATED BENEFITS/POTENTIAL COMMERCIAL APPLICATIONS - A HIGH-DENSITY CCD CHIP THAT CAN AT ONCE SERVE REAL-TIME APPLICATIONS AND SINGLE-OUTPUT-TAP APPLICATIONS WOULD INCUR ONLY A SINGLE NRE CHARGE AND RIDE ON THE PRODUCTION VOLUMES OF BOTH. WE INTEND TO ACTIVELY MARKET PRODUCTS ARISING FROM THIS RESEARCH.