SBIR/STTR Research Award

Fast, Self-Recovery, Fully Rad-Hard FPGA Chip

Award identifier 40875fa5bf82a370deaf814d6a11a1e600fabdc43f0caaec9c6c933a51ab9a3aAwarding agency Department of Defense · Navy

Award amount

$899,964

Program and phase

SBIR · Phase II

Award year

2025

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Award details

Awarding agency
Department of Defense
Branch
Navy
Recipient company
LEWIZ COMMUNICATIONS, INC.
Proposal award date
2025-04-04
Contract end date
2026-10-05
UEI
CXVDG7SBHFN3
Solicitation number
23.1
Topic code
N231-073

Research abstract

As silicon technology moves to deep nano-meter process, the trend for FPGA companies is to concentrate on commercial products and moves away from developing large FPGA chips specifically for radiation hardened (RH) applications requiring high radiation dosage.  The volume of rad-hard chip market is small relative to the commercial sector.  Newer FPGA chips are only offered as radiation tolerant (not Rad-Hard) and will not meet the Navy topic requirements for dosage, latch-up threshold, or circumvention and recovery time. As the trend continue, it’s unlikely large RH, high TID FPGA device will exist in the near future.  This is a potential national security issue. The problem further exacerbated as deep-nano meter silicon fabs currently do not offer RH silicon process – mainly due to economic reason. In Phase 1, LeWiz developed an RH-FPGA-Core that can meet and exceed DoD strategic rad-hard requirements and providing Circumvention & Recovery (C&R) time orders of magnitude better than any available FPGA device. In Phase 1 Option, LeWiz further developed an RH-FPGA-Chip using the RH-FPGA-Core. We also reduced project risks by performed the first part of chip physical implementation using US trusted fab GF12LP silicon process and providing multiple boot options as back up plan for the device. This proposal for Phase 2 will complete the physical implementation, tapeout the device as a test vehicle for the RH-FPGA-Chip in Phase 2 Base and validate the chip in Phase 2 Option.  RH-FPGA-Chip will meet or exceed the Navy requirements and suitable for deployment to strategic applications and space missions. Its FPGA fabric can be scaled to much larger size without compromising the C&R time.  Furthermore, the RH method used for this chip can be applied to more advanced silicon node without requiring RH silicon process - future proof the Navy investment.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

12 SBIR/STTR records share this UEI (2020–2025). Reported award amounts total $5,515,117. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: National Aeronautics and Space Administration, Department of Defense

Agency intelligence

Department of Defense

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