Development of a Time-Triggered Ethernet Intellectual Property Block

LeWiz Phase 1 market research showed that NASA is the leader in applying time-triggered Ethernet (TTE) ¢ an SAE AS6802 standard for aerospace applications. NASA uses TTE in the Orion module and other Lunar vehicles and equipment. Sikorsky/Lockheed has implemented TTE in its future vertical lift helicopter DefiantX. Boeing, Airbus used TTE in control systems for aircrafts. Other companies also applied TTE to industrial control applications. TTE network can carry time-critical information as well as rate-controlled or normal best-effort Ethernet traffic ¢ eliminates the requirement of multiple networks on board aircrafts and reduces weight and power for aerospace systems. It also provides ultra-low latency delivery for critical data and has inherent fault tolerant capabilities. TTE solutions, however, are primarily supplied by a foreign company. The Navy and other DoD agencies require US based solutions. LeWiz is currently working with NASA to develop high speed, multi-port, FPGA based, TTE switching solutions which will be tested with NASA equipment for potential deployment on Lunar systems. In the Navy Phase 1 work, we developed an IP core for TTE (TT Core) targeting 10/100/1000Mbps speeds. We also reduced risk for Phase 2 by (1) implementing a system-on-chip (SoC) design in FPGA to test the full SoC device with software in real network; (2) synthesized the TT Core design in 2 silicon processes (SkyWater RH90nm and Global Foundries (GF) 12LP) using professional silicon tools and simulated the gate-level netlists to verify against RTL results - thereby, validated the whole front end silicon design process (tools, libraries, scripts, etc.) and ensuring functionality. (3) tested for compatibility with space network equipment - i.e., testing in real operational environment, ensuring the success of the Phase 2 and eventual field, operational deployment. We further reduced project risk (i) by using IP cores such as RISC-V CPU that had been successfully taped out with GF 22nm silicon process multiple times previously; (ii) have back-up plan for each major part of the SoC ASIC in Phase 2. For the Phase 2, we propose (i) to use TT Core to develop an ASIC with reference design and software that can be used in TTE endpoint systems; (ii) to validate the ASIC and technologies. This endpoint ASIC together with the switching solution from our NASA works will provide the Navy with a complete TTE solution for deployment in either endpoint or switching applications. The ASIC would be implemented in deep nano-meter silicon process specified by the Navy, using trusted fab. This proposal will provide the Navy with a comprehensive solution to use from TTE endpoint to switching systems ¢ end-to-end network