Performance Optimization of Low-Power Asynchronous Digital Circuits

Asynchronous circuits offer the potential for significant power savings over traditional clocked logic. We propose to develop a tool that would enable design of such low-power circuits without sacrificing circuit speed. We will DELIVER a functional prototype tool during Phase I. The Phase II tool will support VHDL as a hardware description language. The tool capabilities will include transistor optimization that maximizes the circuit speed under power constraint in order to achieve low-power operation, and automatic layout of the resulting circuit. The tool will be tightly integrated into our existing commercial suite of low-cost component-level IC design and synthesis tools. The tool will be targeted towards fully static circuits obtained through a novel self-timed synthesis methodology. These circuits have been shown to operate robustly with power supply voltages less than 1V. Together with the inherent power advantages of asynchronous circuits, this power supply flexibility permits a wide tradeoff of operating speed versus power consumption, in the field. During Phase I we will design the circuit optimization and automatic layout software, develop key components of a prototype design tool, and fabricate test ICs designed with the tool. The Phase I design and prototype prepares for Phase II implementation of the complete system.