Hardware Segmentation and Compression of Video Objects Using Thin Film Analog Image Processors

"In Phase II, CSC proposes to investigate the potential computational gains and compression capabilities of two spatio-temporal approaches to video compression. First, a motion energy segmentation algorithm will be developed for an object-based compressionscheme. Second, a multi-resolution approach will be investigated for a rate-scalable compression scheme. Both methods will be based on the hardware realization of CSC's existing motion-energy image processing system using Thin Film Analog Image Processor(TAIP) spatial filtering chips in combination with temporal frequency band-pass filtering developed under DARPA/BMDO and SMDC funding.During Phase I, CSC investigated methods for performing block-based motion estimation using the TAIP spatial and temporal filtering chips. Block-based motion estimation is used by several existing video compression standards. Although it is possible touse the spatio-temporal architecture to do block-based motion estimation, the results showed that such an approach would not be practical or efficient. The proposed approaches take much better advantage of the strengths of the TAIP architecture and offersignificant compression advantages."