Low-Cost Integration Circuit Manufacturing Using Shared-Mask Gate Arrays

We propose to design and develop a system of manufacturing integrated circuits in small and medium volume using shared masks. Current gate array manufacture dedicates high cost masks to each chip design. For high volumes, this cost is acceptable because it is amortized over a large number of chips. For typical small DoD volumes, the tooling costs make the chips' unit cost 10 to 100 times the high volume unit cost. Our method shares common mask and fabrication costs among 10 to 100 different designs, thus dramatically reducing the cost of each design. Shared mask technology has been successfully used for years by the ARPA-funded MOSIS service, but shared mask technology has never been applied to produce low cost gate arrays in low volumes. Our Phase I effort will include the design, fabrication and testing of sample gate arrays, and the investigation of two advanced concepts. The first idea leads to increased flexibility of the size of gate arrays and therefore reduces the startup costs of the shared-mask gate array manufacturing process. The second idea targets the lowering of costs for medium volume fabrication runs. Phase II will include a full-scale multi-project gate array fabrication run and transition to a Phase III commercial service providing the Navy and commercial customers with low-volume gate arrays at less than 1/10th their current cost. This effort is a follow on to an ONR-funded Phase I and will be geared toward transferring the technology to Navy fabrication facilities.