Development of Analog Mixed Signal IP Library ? for IR FPA ROIC Sensors?

á á SWIRLabs is proposing an alternative approach to ROIC analog block IP generation that overcomes real-world practical limitations to the usefulness of a standard analog IP library.á This approach will provide the benefits of low-risk and low-cycle time of proven IP while still providing block performance optimized to the sensor design specifications.á á The team at SWIRLabs has collectively participated in 100+ tapeouts of custom designed commercial image sensors and read-out integrated circuits (ROICs) targeting a wide range of foundry processes and a diverse set of specifications.á áWhile developing an internal IP library to support these tapeouts, we have learned some of the fundamental challenges of design re-use specifically in ROICs and image sensors.á á In practice, most sensors have unique requirements (e.g. process technology, array size, unit cell pitch, performance specifications, clock speeds, etc.) that preclude direct schematic and layout re-use.á Designing around existing IP tends to restrict design options and typically ends up in compromise on specifications relative to a fully custom, optimized design. áModifying IP ľ even slightly ľ to meet individual sensor specifications is typically done by hand and by highly experienced and specialized design engineers.á These manual adjustments can add months of time and associated costs to sensor development.áá á Technical Abstract: To address the analog IP library and PDK for use in future ROIC designs request, we are proposing to further develop our IP reuse generator-centric design approach. áThe simplified steps to our design reuse flow are 1) take proven schematic templates and re-optimize low level device parameters with codified design testbench procedures (similar to software verification); 2) generate the analog layout with automated scripting; 3) run post layout extraction and re-run the same codified design testbenches for final verification. áThe goal for the entire flow as well as each step is to be more ôsoftware likeö, minimize human intervention, and maximize automationáAs an example, ROICs typically have the same column parallel ADC readout architecture, but the number of columns in an array, ADC resolution or conversion speed may change.á This in turn would require a new set of parameters for the supporting analog ramp generator, such as higher bandwidth or lower noise. áIn our proposed IP generator flow, we would re-use our proven architecture schematic template and ôre-generateö a new IP block that has optimized the bandwidth of the ramp generator to the new set of design specification.á Because the ôre-generationö process has been converted to a systematic codified procedure, the design cycle time, cost and human error risk is significantly reduced.