Evolution of 3GEN+ Advanced Process IP

Most readout integrated circuits in use today use legacy foundry processes that will be at risk of obsolescence in the future. New processes that use smaller design geometries are being developed to facilitate the manufacture of advanced readout ICs in the United States. These more advanced processes will enable lower power consumption, higher operating speeds and smaller die size.Senseeker is currently in the process of designing IP test chips for advanced DPROIC circuitry in two small geometry processing nodes. The creation of these test chips will accelerate the availability and reduce the risk of implementing new advanced DPROICs in these advanced process geometries with more longevity and higher performance. Senseeker proposes to thoroughly test both of these test chips as part of this SBIR Phase I effort. Performance analysis and comparison of the test chips will enable us to optimize the IP blocks in preparation for further test chip runs of advanced DPROIC IP maturity and process down-select in a follow-on Phase II, should we be awarded.Most readout integrated circuits in use today use legacy foundry processes that will be at risk of obsolescence in the future. New processes that use smaller design geometries are being developed to facilitate the manufacture of advanced readout ICs in the United States. These more advanced processes will also enable lower power consumption, higher operating speeds and smaller die size.áSenseeker has previously developed high-performance digital pixel readout integrated circuits (DPROICs) in a larger geometry process that have proven to greatly enhance the performance of infrared imaging systems. A disadvantage of implementing DPROICs in the larger geometry process is that their power consumption and silicon die size is too high and too big, respectively, to reuse existing Dewars and packaging.áWe have therefore developed an approach to greatly reduce power consumption and silicon die area, as well as enhance performance further in several areas, with a goal to completely eliminate roadblocks to DPROIC-based sensor adoption in future platforms. Such an implementation requires a manufacturing improvement in the form of a smaller geometry CMOS process.During Phase I, Senseeker will with prepare and perform detailed advanced DPROIC IP testing using the test chips. We will also conduct a process trade study comparing key performance characteristics between IP blocks on the first set of the new smaller geometry test chips. This and further testing and comparison of revised test chips in Phase II will provide a clear head-to-head comparison of the pros and cons of implementing a next generation DPROIC in these processes and empower us to down-select the process for the next generation readout.