EXPEDITOR: Extensible & Portable, Easy to Deploy IP for Thermal-band Optical ROICs

Most contemporary Readout Out ICs (ROICs) for infrared (IR) Focalplane arrays (FPA) are fabricated using 180nm process nodes, a process technology that is over two decades old. SAAZ team members started designing CMOS Image Sensors and ROICs in Tower/Jazzĺs 180nm node in 1999, when that technology was at the cutting edge. By 2024, the semiconductor industry has progressed 12 generations forward. Each new generation is introduced roughly every 18 months, scaling the process technology by ?2. The 3nm technology is the latest generation in production. For example, Intel announced that it is ramping up 3nm production in its Oregon facility this summer. These newest generation processes are extremely expensive and appropriate for high volume digital ICs, but ROICs also greatly benefit by process scaling when moved to contemporary nodes ideally suited for mixed-signal ICs, such as the 65nm ľ 90nm processes.ááThe 90nm-65nm nodes offer the following benefits for ROICs: (1) pixel size can be reduced, scaling down die, optics, and system cost, (2) higher density nodes enable more complex features to be integrated on chip, and (3) digital power halves with each process generation, reducing chip power. SAAZ has been commercially funded since 2017 to develop several ROICs in the 90nm/65nm processes. Through our experience we are aware of several issues with fully migrating to these nodes, such as (1) mask costs, as these masks cost 5x ľ 10x of the 180nm masks, and (2) the design complexity in these nodes, which requires advanced tools and significantly longer design cycles.ááSAAZĺs proposal addresses these technology adoption issues by developing reusable IP blocks for ROIC design. Since the design cycles in 90nm/65nm nodes are long and design iterations are expensive, it is imperative that ICs in these technologies be built by assembling ROICs from known good building-block IP components. This approach shortens the design and verification cycle and greatly increases the chances of first-pass success. Large programs, such as those funding SAAZ to develop 65nm/90nm ROICs, can afford the full cost of these new developments but all programs, including SBIRs, will be able to afford advanced node developments once such IP is available.áSAAZ proposes to offer the IP as soft IP, hard IP and golden IP. Soft IP would contain analog schematics and digital circuit code that is fully characterized through simulations for a process but is portable to other processes. Hard IP would contain a layout block that has gone through parasitic extraction, optimization, and LVS/DRC/DFM checks. This IP would be ready to drop into an IC layout. Golden IP will have a silicon characterization report and can be incorporated without any further verification.ááStarting with existing reference designs, we will develop and deliver the most in-demand, useful and highest risk IP components identified in collaboration with stakeholders, following our rigorous development methodology.