HIGH-PERFORMANCE ANALOG CMOS CONVOLVER

RESEARCHERS ARE DESIGNING AND FABRICATING A HIGH-PERFORMANCE CONVOLVER INTEGRATED CIRCUIT, THAT CAN BE COUPLED TO A DIGITAL STOCHASTIC NEURAL NETWORK CLASSIFIER. THE ARCHITECTURE HAS A PREDICTED SINGLE-CHIP PERFORMANCE OF 50 BILLION MULTIPLY/ACCUMULATES PER SECOND. UNLIKE COMPETING NEURAL NETWORK INTEGRATED CIRCUITS, THIS THROUGHPUT CAN BE MAINTAINED WITH REALISTIC CHIP I/O BANDWIDTHS. THIS HIGH PERFORMANCE IS ACHIEVED AT THE ARCHITECTURE LEVEL BY EXPLOITING MASSIVE PARALLELISM IN COMPUTING SEVERAL CONVOLUTION KERNELS SIMULTANEOUSLY, AND AT THE CIRCUIT LEVEL BY USING COMPACT MULTIPLYING D/A CONVERTERS (MDACS) AND ANALOG CURRENT SUMMING. RESEARCHERS ARE DEVELOPING CUSTOM INTEGRATED CIRCUITS THAT SUPPORT THE CONSTRUCTION OF LARGE, HIGH PERFORMANCE NEURAL NETWORKS. THE EFFORT INCLUDES THE DESIGN AND FABRICATION OF A SMALL-SCALE PROTOTYPE CMOS INTEGRATED CIRCUIT TO PROVE THE FEASIBILITY OF THE DEVELOPMENT. THE APPROACH UTILIZES COMMERCIAL CMOS/BULK INTEGRATED CIRCUIT TECHNOLOGY. PRODUCTS ARISING FROM THIS R&D CAN BE FABRICATED RELIABLY AND ECONOMICALLY BY A NUMBER OF VENDORS.