PARALLEL OUTPUT IMAGING SENSOR

WE PROPOSE TO INVESTIGATE AND DEVELOP A PARALLEL OUTPUT IMAGING SENSOR BASED ON A CUSTOM MOS INTEGRATED CIRCUIT. THE SENSOR WILL HAVE AN IMAGING RESOLUTION OF APPROXIMATELY 256 X 256 PIXELS AND OPERATE AT FRAME RATES GREATER THAN 2000 FRAMES/SECOND. THE HIGH BANDWIDTH REQUIREMENTS WILL NECESSITATE PARALLEL OUTPUTS FROM THE CHIP, PERHAPS AS MANY AS ONE OUTPUT PER ROW OF SENSORS. OUR APPROACH WILL UTILIZE STANDARD READILY AVAILABLE CMOS BULK INTEGRATED CIRCUIT TECHNOLOGY SO PRODUCTS ARISING FROM THE R&D CAN BE FABRICATED RELIABLY AN CHEAPLY BY A NUMER OF VENDORS. WE HAVE DEMONSTRATED THE FEASIBILITY OF FABRICATING PHOTOSENSOR ARRAYS USING STANDARD CMOS PROCESSES. A SMALL CIRCUIT ASSOCIATED WITH EACH PHOTOSENSOR IN THE ARRAY PROVIDES A LOGARITHMIC OUTPUT THAT EXTENDS THE DYNAMIC RANGE OF LIGHT INTENSITIES TO GREATER THAN 10,000. OUR ASSOCIATES AT CALTECH HAVE BUILT AND DEMONSTRATED CMOS SCANNING ARRAYS AT NORMAL VIDEO RATES. THE DEVELOPMENT OF A HIGH SPEED PARALLEL OUTPUT VIDEO CAMERA IS A NATURAL EXTENSION OF THIS PRIOR WORK AND LEADS DIRECTLY TO AN INEXPENSIVE PRODUCT WITH WIDE APPLICABILITY IN COMMERCIAL, ACADEMIC, AND MILITARY MARKETS.