Radiation Hardening of an Asynchronous Multi-layered Sensor Processor

The objective of this proposal is to develop an analog design concept for gamma spike noise correction of continuously sampled INFRARED detector data. The radiation tolerance benefits resulting from a multi-layer sensor/processor system approach is theelimination of the detector charge integration capacitor from the front-end of the data processing sequence where latch-up or charge dumping failures due to gamma absorption have the greatest deleterious impact, and the real-estate savings arising fromremoving gamma deletion and other image processing circuitry out of the detector unit cell enabling increased spatial resolution in the same array footprint. This effort supports Computational Sensors Corporation's (CSC) program to develop an asynchronous,continuously sampled, multi-layer stacked sensor/processor technology. This concept envisions the direct conduction of photocurrents into stacked resistive grids for direct image processing. Such a device structure has the potential to operate continuouslyand utilize all collected photons as opposed to the disadvantage of contemporary focal plane technologies that have limited dynamic range due to well capacity limitations of direct injection approaches. CSC envisions an ionizing radiation tolerantmulti-layer architecture in the analog domain, which maintains the intrinsic IR FPA detector dynamic range and integrates non-uniformity correction with spatio-temporal filtering into a single device. The technology that emerges from this effort willenable the first new architectural approach to the readout of staring focal plane sensors, since their invention in the early 1970's, by providing continuous parallel image processing without synchronous multiplexed operations. To accomplish thedevelopment of a multi-layer stacked detector sensor/processing, data correction tasks including gamma radiation tolerance and detector NUC correction must be developed in concert with the effort to develop image processing layers. Target analysiscapabilities using non-linear motion energy image processing techniques integrated in Analog VLSI image processors are ideally suited for compact, low power, military applications. The scene motion analysis approach is described in the Technology Reviewsection. The company's primary goal is to move this core technology into the military market with products using this technology initially be sold to military guidance and control applications.Analog VLSI image processing technology may also be applicable in many other commercial areas including automatic inspection, biometric identification, security, surveillance, and other machine vision applications. To date, non-linear motion energy imageprocessing technology using TAIP chip technology developed under Defense Advanced Research Projects Agency (DARPA) contract in conjunction with temporal filtering capability developed under MDA and ARMY Space & Missile Defense Command (ARMY-SMDC) contracthas demonstrated significant utility in detection, track-before-detect capability when coupled with dynamic programming, and discrimination of low flying missile targets in moving background clutter. CSC is fulfilling current DARPA and AtmosphericInterceptor Technology (AIT) sponsored contracts while aggressively pursuing potential commercial opportunities for analog VLSI image processing applications. The unique and powerful capability to perform massive convolution functions in real-time, in asmall package and with low power requirements will enable a new generation of intelligent systems not previously considered viable by system and product designers systems for performing sophisticated imaging tasks including automatic target recognition,target tracking, feature extraction, 3D reconstruction, image classification, and image understanding are critical for the building of compact, low powered deployable missile defense systems.