SBIR/STTR Research Award

Real-Time Hardware Configurable Coprocessors

Award identifier e05f14dbd75223b4ebc32b283885963862da34ecf44d0848a9ef286a86042549Awarding agency National Aeronautics and Space Administration

Award amount

$899,999

Program and phase

SBIR · Phase II

Award year

2024

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
RESILIENT COMPUTING, LLC
Proposal award date
2024-06-13
Contract end date
2026-06-12
UEI
KN4SRR3AFM17
Solicitation number
SBIR_23_P2
Topic code
Z2

Research abstract

This project will prototype a coprocessor companion for radiation-hardened computers that can boost system performance by exploiting the parallel resources and reconfigurability of commercial Field Programmable Gate Arrays (FPGA). The prototype builds upon a feasibility study that investigated using dynamically reconfigurable coprocessing circuitry integrated into a proven fault-tolerant architecture known as RadPC.nbsp; The RadPC architecture has been matured through NASA-funded flight demonstrations at Montana State University culminating with a lunar mission in 2024.nbsp; RadPC was licensed to Resilient Computing in 2021 to bring it to market as a viable aerospace solution.nbsp; Through prior NASA SBIR funding, RadPC has been adapted and matured into a form that uses the emerging RISC-V CPU, implements fault-recovery procedures abstracted from the developer, and supports inclusion of coprocessors within the fault-tolerant architecture. nbsp;In this project, we will prototype a coprocessor system that can be dynamically configured using the partial reconfiguration (PR) capability of modern FPGAs.nbsp; This approach enables more efficient use of FPGA resources by implementing signal processing algorithms as a sequence of tasks accomplished with different processing blocks that are swapped in and out while holding the interim results in the fast storage registers of the coprocessor.nbsp; By swapping the processing blocks using PR, the hardware resources needed on the FPGA is reduced because not all the steps of the algorithm are implemented simultaneously.nbsp; This leads to faster computation by reducing delays on the FPGA and less power consumption due to using less circuitry at any given time.nbsp; The proposed prototype will perform object detection on incoming camera data using a sequence of coprocessor steps that are dynamically swappable including filtering, edge detection, and pattern recognition.nbsp;The prototype will undergo fault-injection testing and two rounds of radiation testing.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

6 SBIR/STTR records share this UEI (2021–2024). Reported award amounts total $2,394,499. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: National Aeronautics and Space Administration, Department of Defense

Agency intelligence

National Aeronautics and Space Administration

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