Real-Time Hardware Configurable Coprocessors

This project proposes a coprocessor companion to future radiation-hardened processors that can boost performance using commercial Field Programmable Gate Arrays (FPGA). nbsp;This project will investigate the feasibility of using dynamically reconfigurable coprocessing circuitry within a proven fault-tolerant architecture known as RadPC.nbsp; The RadPC architecture has been matured through NASA-funded flight demonstrations at Montana State University culminating with a lunar mission in 2024.nbsp; RadPC was licensed to Resilient Computing in 2020 to bring it to market as a viable aerospace solution.nbsp; Through prior NASA SBIR funding, RadPC has been adapted and matured into a form that uses the emerging RISC-V CPU, implements fault-recovery procedures abstracted from the developer, and supports inclusion of coprocessors within the fault-tolerant architecture. nbsp;In this project, we will study how the coprocessor circuitry can be dynamically configured using the partial reconfiguration (PR) capability of modern FPGAs.nbsp; This approach enables more efficient use of FPGA resources by implementing signal processing algorithms as a sequence of tasks accomplished with different processing blocks that are swapped in and out while holding the interim results in the fast storage registers of the coprocessor.nbsp; By swapping the processing blocks using PR, the hardware resources needed on the FPGA is reduced because not all the steps of the algorithm are implemented simultaneously.nbsp; This leads to faster computation by reducing delays on the FPGA and less power consumption due to using less circuitry at any given time.nbsp; This project will investigate whether the latency of swapping the PR blocks outweighs the speed up in computation and if this approach is feasible for the types of signal processing algorithms needed for future space missions.