Fault Tolerant Computing based on a Reconfigurable Hardware/Software Architecture

Computers that operate in space are exposed to a harsh radiation environment that causes material degradation and intermittent crashes.nbsp; Current solutions to this problem include ldquo;hardeningrdquo; a computer by altering the underlying semiconductor material and using non-standard circuit designs.nbsp; These approaches make these rad-hard computers expensive and with performance that lags commercial computers by ~20 years.nbsp; There is currently a demand from the aerospace industry for new computers that can match commercial performance while achieving the reliability needed in a space environment at a price that is not cost-prohibitive for the wide-scale adoption.nbsp; This project builds on over 10 years of NASA-funded research at Montana State University on a computer architecture called RadPC.nbsp; RadPC implements a comprehensive set of fault mitigation strategies on a commercial Field Programmable Gate Array (FPGA).nbsp; Various sub-systems of RadPC have been demonstrated on high-altitude balloons (8x), on sounding rockets (2x), on the International Space Station, and on two small satellite missions.nbsp; RadPC has also been selected for a lunar surface demonstration through the Artemis program.nbsp; Through this past research, the architecture of RadPC has been refined into one that achieves the performance, reliability, and flexibility to support future space missions.nbsp; However, the current prototype form of RadPC requires manual construction of the system at each step of the design process.nbsp; This manual and tedious construction of the current RadPC system makes it difficult for RadPC to be adopted as a commercial product.nbsp; The aim of this SBIR project is to investigate the automation of the development process for RadPC so that a developer can write programs for the RadPC architecture without being burdened with the underlying fault mitigation procedures that are being implemented.