Fault Tolerant RISC-V Flight Computer with Coprocessor Support

This project aims to mature an innovative approach to advance the state-of-the-art in high performance space computing through the development of a fault tolerant RISC-V flight computer with coprocessor support.nbsp; This project builds on over 14nbsp;years of NASA-funded research at Montana State University (MSU) on strategies to provide fault tolerance in space computers through the implementation of a novel self-repairing computer architecture on Commercial-off-the-Shelf (COTS) Field Programmable Gate Arrays (FPGAs).nbsp; The MSU technology, called RadPC, was licensed to Resilient Computing in 2021 to move it closer to commercialization.nbsp; Under funding from a 2021 NASA SBIR Phase I award, Resilient Computing conducted customer discovery on the RadPC concept and refined the computer concept to be closer to a viable product through an in-depth feasibility study on how software-implemented fault tolerance (SIFT) could be automated in the RadPC approach.nbsp; In this project, we seek to study the feasibility to automating SIFT for a RISC-V computer system implemented on the RadPC fault-tolerant, FPGA-based flight hardware.nbsp; We further seek to refine the architecture to support the seamless integration of RISC-V coprocessors that both accelerate computation and are fault-tolerant using the same RadPC strategy implemented on the primary RISC-V computer.nbsp; The outcome of this Phase I effort will be a conceptual design for a RISC-V flight computer with coprocessor support that will be prototyped in a subsequence Phase II project.