Radiation Hardened Time Triggered Ethernet IP

As a response to NavyÆs Navy SBIR Topic N221-080, Alphacore will develop a radiation hardened Time-Triggered Ethernet (TTEthernet) Intellectual Property (IP) block for hard real-time control applications in next-generation avionics architectures. This proposed work will integrate AlphacoreÆs advanced radiation hardened physical layer (PHY chip) with network level radiation hardened TTEthernet protocol implementation. The proposed system will be designed to be implemented on GlobalFoundriesÆ 22nm Fully-Depleted Silicon-on-Insulator (FD-SOI) fabrication platform called GF22FDX. A GF22FDX test chip will be fabricated, tested, and demonstrated by the end of Phase II. Based on discussions with GlobalFoundries, the GF22FDX process will be available on-shore in 2024, before our tapeout date. There is also a plan to have a radiation-hard GF22FDX variant ¢ called GF22FDX-RH ¢available and on-shore towards the end of this program.Ā Objectives for the proposed Phase II are: Objective 1) Optimize TTEthernet IP for ASIC implementation. Objective 2) Complete a selected set of radiation hard standard cells in GF22FDX. Objective 3) Optimize PHY. Objective 4) Integrate TTE IP and PHY on an ASIC test chip and send it to fabrication. Objective 5) Package and test. Objective 6) Radiation Test the fabricated test chips.