Scalable IP for Time-Triggered Ethernet Avionics

To address the Navy need for a custom intellectual property (IP) block for Time-Triggered Ethernet (TTE), Intellisense Systems, Inc. (Intellisense) proposes to develop a new Scalable IP for Time-Triggered Ethernet Avionics (SIPTEA) solution based on the combination of standards-based interfaces supported by novel time-triggered network calculus techniques and algorithms and novel modular architecture features supporting future capability growth with minimal redesign. Specifically, the innovation in novel network calculus algorithms for performance optimization and the use of open architecture principles for scalability and adaptability enable SIPTEA to exceed the performance of existing commercial TTE systems. As a result, the proposed SIPTEA solution directly addresses the Navy’s need for a trusted and validated TTE IP block for incorporation into next-generation avionics architectures. The strict conformance to the SAE AS6802 and IEEE 802.3 standards and requirements ensures compatibility with existing test systems and suites. In Phase I, Intellisense will provide a proof-of-concept IP block that implements endpoint functionality and can support at least 10 Mpbs. The demonstration will be leveraged to provide a path towards synthesis on a technology node along with verification of the design and development of initial design specifications for prototyping. In Phase II, we will fabricate a validation integrated circuit with verification suite that will be tested to meet the performance requirements and be made available to the Navy. This will lead to Phase III support for transitioning the IP to deployment with the Navy and exploring the commercialization of the technology for commercial rocket and space sectors, as well as commercial avionics.