SBIR/STTR Research Award

High Multi-speed Time-Triggered Ethernet

Award identifier 0f4b55caa5d8371348936557e2d3abd38215d182f502eb0f9a410fe9a2851002Awarding agency National Aeronautics and Space Administration

Award amount

$159,990

Program and phase

SBIR · Phase I

Award year

2022

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
LEWIZ COMMUNICATIONS, INC.
Proposal award date
2022-07-19
Contract end date
2023-01-25
UEI
CXVDG7SBHFN3
Solicitation number
SBIR_22_P1
Topic code
Z2

Research abstract

Time critical data requires low latency and deterministic transfer. Sensor, command and control data of mission-critical, high-reliability, real-time applications such as collision avoidance, avionics require on-time delivery. Images from a camera of an autonomous spacecraft to its processing system must be communicated deterministically and low latency for the system to function correctly. Ethernet is ubiquitous. Itrsquo;s being used everywhere from small devices to high performance computing system. Its large ecosystem of products and services provides key advantages -nbsp;low cost, high availability, wide range of available developers and support. However, data transferred via Ethernet is ldquo;best-effortrdquo; and may be buffered. This causes significant jitter and non-deterministic in information delivery timing. Packets transferred may be dropped by Ethernet switches, routers and delivery is not guaranteed.nbsp; Time-triggered Ethernet (TTE) has been specified and standardized by SAE International as AS6802 for aerospace applications overcoming time critical issues in Ethernet and supports fault tolerant (synchronization, handshake, etc.). However, solution for the upper Ethernet speeds with radiation tolerant does not exist. NASA SBIR topic Z2.02 requests for IP core for TTE for use in onboard networks with gt;10Gbps. Proposed is a TTnbsp;IP core with speed 10Gbps and beyond for TT Ethernet with radiation tolerant. It uses a novel architecture that can span multiple speeds, allowing software reuse, ultra-low jitter, implementable in FPGA or ASIC. Designers can configure the design to suit specific application (e.g., routers, switches, high performance endpoints) or available technology. Several immediate applications in NASA and non-NASA have been identified for commercialization. For the long term, this solution is suitable for use in space vehicles, satellites, aircrafts, drones, etc. -nbsp;applicable to NASA, DoD and others nbsp;

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

12 SBIR/STTR records share this UEI (2020–2025). Reported award amounts total $5,515,117. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: National Aeronautics and Space Administration, Department of Defense

Agency intelligence

National Aeronautics and Space Administration

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