Highly-Integrated SiC BiCMOS/Power Device Technology: Design, Modeling, and Reliability Metrics

We propose to lay the groundwork for the implementation of a completely integrated SiC BiCMOS/LDMOS technology for integrated control/power circuit applications reliable for operation up to 300 C. Our workplan to accomplish this goal comprises improving device speed and reliability by device engineering, establishing baseline reliability and qualification tests to support and certify development, and to build on our extensive background in physics-based device design and modeling to guide our designs, to extract models, and to start establishing a process design kit (PDK) for wide-spread application of this technology. CoolCAD Electronics has successfully demonstrated SiC MOSFET operation at temperatures exceeding 400 C, and has an established track-record in process development, including patent-protected processes for an integrated SiC optoelectronics/readout circuit technology. Our device engineering efforts will focus on gate oxide engineering for improving quality and reliability of the oxide and of the SiC/SiO2 interface, which will also improve channel mobility. We will also work to reduce device critical dimensions, especially gate length, for better device speed, and tailor our device designs accordingly. On the reliability front, we will focus on specific metrics including time-zero breakdown and time-dependent dielectric breakdown aspects for the oxides, gate leakage, positive or negative bias temperature instability, and monitoring any other permanent changes in performance as a result of aging tests. We will also identify key factors for yield in preparation for the full process development in Phase 2. We will perform TCAD simulations of key transistor structures, MOSFETs, BJTs and LDMOS devices in particular, to guide our device design in Phase 1 and Phase 2. Using the various TCAD tools at our disposal, some of which developed in-house, we can concentrate on different aspects of device behavior, study fields and carrier concentrations within the device, analyze breakdown characteristics, and fine-tune the doping and structural design elements. Finally, we will use our experience in developing SPICE model cards, for commercial foundries among others, to create BSIM-compatible SPICE models for the MOSFET and LDMOS devices we have previously fabricated. Moving on to Phase 2, the process development and device design performed in the Phase 1, guided by the results of the reliability and characterization studies, will let us design and fabricate monolithically integrated SiC CMOS, BJT and LDMOS devices and circuits, complete with the BSIM-compatible model cards for standardized reliable circuit design using the PDK which will be developed for this fabrication technology.