SBIR/STTR Research Award

Manufacturing Platform for High-Temperature CMOS ICs on SiC

Award identifier b9143cc84a25edb172200f70e4d11710eb0c10a60ed3bc2f3bcc98d91edce603Awarding agency Department of Defense · Defense Microelectronics Activity

Award amount

$156,403

Program and phase

SBIR · Phase I

Award year

2021

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Award details

Awarding agency
Department of Defense
Branch
Defense Microelectronics Activity
Recipient company
NOMIS POWER CORPORATION
Proposal award date
2021-07-29
Contract end date
2022-02-10
UEI
MQKPC5MHRN99
Solicitation number
21.1
Topic code
DMEA211-001

Research abstract

This project aims to develop high-temperature (> 300°C) operational dielectrics for SiC CMOS integrated circuits (ICs) technologies in a production-grade fabrication facility in the U.S. All outcomes of this project will directly benefit future implementations of various kinds of high-temperature electronics for defense applications.Increasingly, the development of SiC CMOS-based ICs that can operate at high temperatures is at the forefront of SiC-based device research. Despite many technical barriers to achieving high temperature operation of SiC CMOS ICs, it is paramount that significant effort be devoted to the development of reliable dielectrics and credible fabrication sources for high-temperature SiC CMOS ICs. Benefiting from the current effort on SiC SMART IC (funded by ARPA-e, issues for SiC CMOS-based circuits when operating at high temperatures will be identified in the beginning of the project. The methodology for pursuing the proposed solutions in this project are unique in that: 1) New process schemes or methodologies will be developed at the proposed production-grade fabrication facility from the beginning, as solutions developed in small-scale cleanroom environments are often difficult to implement successfully in a volume manufacturing facility due to incompatibility; 2) Advanced capability and tool variety at the proposed facility will ensure successful demonstration of newly proposed process technology; 3) High-temperature operations of SiC CMOS-based exemplary circuits will be demonstrated as a goal of this project; 4) While focused on gate dielectric (µn > 50 cm2/V-s,  µp > 10 cm2/V-s, Vth shift < ± 0.5 V) and interlayer dielectric (ILD) processes, other process-related developments such as ohmic contacts and packaging of the ICs will also be pursued for the functional demonstration of high-temperature SiC CMOS FETs; 5) The process baseline for SiC CMOS that is being established in an already existing project will be the basis of the proposed research, which will reduce effort/time for this project, ensuring the chance of success.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

5 SBIR/STTR records share this UEI (2021–2024). Reported award amounts total $1,017,410. Reported amounts are not federal obligations.

Phases: Phase I

Agencies: Department of Energy, Department of Defense, National Science Foundation

Agency intelligence

Department of Defense

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