Highly Parallel, Fast Memory Access for RISC-V Many-Core Processors

High performance computing system requires many-core processor with network-on-chip (NOC) interconnecting the cores. nbsp;A major issue is the competition of the many cores for access to memory. Example of this can be seen in GPU designs. In addition, systems traveled to remote planets perform large data analytic, image processing, autonomous applications remotely. These are not suitable for general cache-based designs, causing cache miss often and thrashing performance. NOC designed for cache system are also not suitable for large data transfers from accelerators of such applications and high-speed peripherals (PCI-express, Ethernet) to memory. Space travel further requiring fault tolerant (FT), ECC capabilities. Current solutions for RISC-V do not address all of these issues. 2021 NASA SBIR topic Z2.02 calls for ldquo;a fault-tolerant RISC-V processor IP core hellip; that is augmented to provide data parallelism, which is needed to accelerate image processing and science data processing.rdquo; LeWiz developed a 64-bit FT RISC-V processor core in a previous NASA SBIR Phase 1 for many-core CPU architecture. This work will enhance its NOC design and implements new, highly parallelized NOC based FT memory controller supporting multi-banks, high bandwidth memory where large number of independent access channels are available, more suitable for large data processing. This augmentation will provide the best, highly parallelized data access for many-core processor using state-of-the-art DRAM technology meeting NASA topic requirements