3D Integrated Memristor Chip for Neuromorphic Processing

Technical Abstract:This SBIR project proposes an integrated, multi-functional and reprogrammable memristor array having a multilayered crossbar architecture to emulate biological synapses in a small scale. Passive memristor crossbar array will be integrated with necessary peripheral circuitry for control of resistance states of memristors for imitating synaptic weights of neural networks. The input-output signals will be modulated using appropriate field programmable gate array (FPGA) control.nbsp; Our proposed work demonstrates a less costly FPGA controlled integrated neuromorphic processor chip design scheme using oxide based memristors and peripheral circuitry from traditional CMOS technology.nbsp; nbsp;The proposed 3D memristor architecture could provide a unique cross-bar array technology with reconfigurable memristors, with the resistance states of memristors controlled using an FPGA.nbsp; The FPGA based system would allow for precise programming of the memristors for the training, and the available computing and memory resources for inferencing.nbsp; The innovation is in the design and fabrication of oxide thin film based memristors for each layer, with some of the memristors exhibiting large off/on resistance ratios, some used for switching, and some with low off/on resistance ratio with large number of intermediate resistance states (depicting the synaptic weights).nbsp; Innovative fabrication and packaging solutions will be considered in Phase 2 for developing a microsystem with unique low power neuromorphic computing capability with SWaP considerations for small satellites.nbsp;