SBIR/STTR Research Award

Energy Efficient High-Throughput Neuromorphic Processor for Deep Learning

Award identifier 2a199812b6c9b09081e9c258373758c4dfce0b1c22864a0e47519bf1bf875df3Awarding agency National Aeronautics and Space Administration

Award amount

$749,862

Program and phase

SBIR · Phase II

Award year

2020

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
PRIXARC LLC
Proposal award date
2020-07-02
Contract end date
2022-07-01
UEI
F4N3H1J8CDC8
Solicitation number
SBIR_19_P2
Topic code
H6

Research abstract

The technical objective of this work is to develop a low power, high throughput neuromorphic system for online learning. The system will be based on an FPGA to enable low cost development and easy deployment. We propose to implement a transfer learning system as this will allow the FPGA to train a convolutional neural network with new data quickly and without significant hardware resource requirements. The system will be integrated with a software defined radio to be able to collect communications data continuously to be utilized for transfer learning. We have developed a prototype of the FPGA based transfer learning system in Phase I and aim to make the system more efficient, scaled up, more accurate, and general purpose so that it would be more adept at learning cognitive communications modulations in a cubesat environment. In addition to the FPGA based online learning system, we will investigate the design of accurate and efficient deep learning algorithms for the FPGA system to process cubesat communications data. This dual pronged approach of developing hardware and software will lead to the most efficient overall system, having low power, high accuracy, and high speed. We will integrate the system with a software defined radio to mimic satellite communications and carry out field tests of the system to ensure proper reliability and functionality. Our key deliverables will be the FPGA system design, deep learning algorithm evaluation and best algorithm for cognitive communications learning on the FPGA, and software defined radio integration of the FPGA system.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

17 SBIR/STTR records share this UEI (2018–2024). Reported award amounts total $6,275,539. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy

Agency intelligence

National Aeronautics and Space Administration

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