SBIR/STTR Research Award

Energy Efficient High-Throughput Neuromorphic Processor for Deep Reinforcement Learning

Award identifier 708b0f004de2c11efe450b2dfb81c182fab6a5d9c06037326a525d82c5a8c733Awarding agency National Aeronautics and Space Administration

Award amount

$124,599

Program and phase

SBIR · Phase I

Award year

2019

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
PRIXARC LLC
Proposal award date
2019-08-19
Contract end date
2020-02-18
UEI
F4N3H1J8CDC8
Solicitation number
SBIR_19_P1
Topic code
H6

Research abstract

In space environments, particularly for low powered satellites (such as cubesats), onboard neural processing has many applications. One of the key neural algorithms that would be highly useful is reinforcement learning for cognitive communications in software-defined radios. In reinforcement learning a policy function is used for determining action and needs to be updated based on environmental inputs. This function can become extremely complex and is often approximated using deep learning networks, thus leading to deep reinforcement learning algorithms. The updating of these deep networks themselves can be highly energy consuming. At present there are no low SWaP, high throughput deep reinforcement learning processors available commercially. Thus the objective of this work is to develop highly efficient neuromorphic processors for deep reinforcement learning, particularly for cognitive communications. In this work we will examine application properties of deep reinforcement learning algorithms in terms of their hardware requirements, and then make efficient hardware for them. A key component of this work will be to make highly energy efficient processors for training deep learning networks ndash; this is the most computationally demanding task of the algorithm. We will look at multiple design options and evaluate their performance for several deep reinforcement learning based cognitive communications datasets. We will select the best architecture option for prototyping as a scale down version an FPGA for verification. This work builds on very extensive work we have done in the past on efficient processors for training deep networks. In Phase II we will design a full chip based on the best option in Phase I and characterize its performance. We will collaborate with researchers at NASA Glenn and at AFRL for this work. The chip will have many commercial applications, including cubesats, UAVs, commercial and personal radio communications, and big data applications.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

17 SBIR/STTR records share this UEI (2018–2024). Reported award amounts total $6,275,539. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Aeronautics and Space Administration, Department of Energy

Agency intelligence

National Aeronautics and Space Administration

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