SBIR/STTR Research Award

SBIR Phase I: Radiation Hardened Integrated Circuits for CT Scanners with Reduced Radiation Exposure

Award identifier db7345ecbd907c1c3ea633839eb96a2ae5911dba35ed3cb75b35c7f2125a9ddfAwarding agency National Science Foundation

Award amount

$150,000

Program and phase

SBIR · Phase I

Award year

2014

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
APOGEE SEMICONDUCTOR, INC.
Proposal award date
2014-01-01
Contract end date
2014-06-30
UEI
SQ3NLYSGDAW7
Solicitation number
Not reported
Topic code
EI

Research abstract

This Small Business Innovation Research (SBIR) Phase I project targets development of a radiation-hard IC design technology at the transistor level. This will enable the design and production of radiation-hard devices using standard CMOS processing, with an order of magnitude improvement in radiation tolerance compared to standard transistor designs. The proposed approach uses innovations in IC transistor design and layout methods which, while maintaining the performance of standard CMOS integrated circuits, greatly increase their radiation tolerance. The ability to use existing advanced CMOS IC designs and processes will enable better performance from the electronics and extend electronics life in high-radiation applications. An early application of this technology will be the signal processing electronics used in CT scanners, with an objective of reducing radiation exposure experienced by patients and medical personnel during CT scans. This project will enable production of sensor signal processors that could be positioned as close to the X-ray detectors as desired, directly in the X-ray beam path, and ultimately integrated with detectors. The objective of this Phase I project is to provide proof-of-concept of methods to greatly improve the radiation tolerance of integrated circuits in designed in standard CMOS, for use in CT-scanner electronics and other high-radiation applications. The broader impact/commercial potential of this project will be to provide CT-scan equipment manufacturers the capability of building CT-scanners offering significantly reduced exposure by enabling the placement of detector electronics in direct proximity to X-ray detector rows. The key to the ability to address the market for CT scan equipment electronics with this improved radiation exposure technique is the ability to design radiation-hard ICs in standard semiconductor processes. This project targets the improvement of IC radiation hardness by the use of design techniques within existing commercial processes, rather than by developing costly new processes. Dose reductions in medical and dental X-rays, body scanners used for national security, and related systems would reduce societal health risks and the incidence of cancer. The project will enhance scientific and technological understanding of radiation effects on CMOS integrated circuits, as well as providing methods to improve their radiation tolerance. Radiation-hard electronics could be more easily developed for a wide range of applications where reliability is essential.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

12 SBIR/STTR records share this UEI (2014–2024). Reported award amounts total $6,475,305. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Science Foundation, National Aeronautics and Space Administration, Department of Energy

Agency intelligence

National Science Foundation

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