SBIR/STTR Research Award

SBIR Phase II: Low-Cost Packaging Solution for Space-Grade and High-Reliability Integrated Circuits

Award identifier 24ecb4ad0a6369f44fd525c5928eaedb5df965df8385e4749c56703c82f54f7aAwarding agency National Science Foundation

Award amount

$999,561

Program and phase

SBIR · Phase II

Award year

2024

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Award details

Awarding agency
National Science Foundation
Branch
Not reported
Recipient company
APOGEE SEMICONDUCTOR, INC.
Proposal award date
2023-12-01
Contract end date
2025-11-30
UEI
SQ3NLYSGDAW7
Solicitation number
NSF 22-552
Topic code
SP

Research abstract

This Small Business Innovation Research (SBIR) Phase II project enables the use of modern packaging technologies for integrated circuits in space applications. While failures in satellites are common and high insurance claims due to such failures are frequent, the space industry continues to use integrated circuits (ICs) that are either unreliable (non-space-grade) and are prone to failure, or space-grade ICs with large and costly packaging and compromised performance. This innovation offers a cost-effective and reduced-size solution for the packaging of ICs that can operate reliably over the extreme temperature cycles experienced in space applications. Wafer Level Chip Scale Packaging (WLCSP) is lighter, smaller, and has superior electrical and thermal performance when compared to traditional leaded packaging solutions. These attributes make it desirable to the space industry by reducing size and weight, while not compromising performance. As this packaging technology is limited due to its performance under temperature cycling, this project seeks to address this reliability problem by using existing manufacturing techniques coupled with a novel design concept. This Small Business Innovation Research (SBIR) Phase II project aims to redesign specific layers within the existing Wafer Level Chip Scale Packaging (WLCSP) to improve reliability under temperature cycling. The temperature cycle reliability problem in the WLCSP is caused by a thermal expansion rate mismatch of silicon die and the copper circuit board. This project will redesign the redistribution layer within the WLCSP to compensate for this mismatch by effectively moving the interconnects on the silicon die in accordance with the faster moving printed circuit board (PCB). This project will make the benefits of WLCSP accessible for the entire space community. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Research funding history

12 SBIR/STTR records share this UEI (2014–2024). Reported award amounts total $6,475,305. Reported amounts are not federal obligations.

Phases: Phase I, Phase II, Phase II – Direct to Phase II

Agencies: Department of Defense, National Science Foundation, National Aeronautics and Space Administration, Department of Energy

Agency intelligence

National Science Foundation

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