Ultra-Dense Three-Dimensional Electronics for Space

Two radiation hardened 3D integrated circuit memory devices will be fabricated under this effort. The 3D devices are created by the wafer level 3D bonding of separate silicon substrates. Within each of the ~200 die in the resultant wafer stack, there some 5 million vertical interconnects. The very high level of 3D interconnect allows unprecedented vertical circuit optimization. In this case the two proposed devices will be fabricated with the same masks and both will share the same memory cell layers that are also used for Tezzaron’s standard commercial memories. This allows not only a cost reduction but also eases commercial production by keeping the non-ASIC portion of the components in common. The core effort in this program is developing a new hardened by design logic layer (wafer) that will improve the circuit reliability for space and military applications. The 3D integration by its nature will also give improve density, power and performance. Without 3D, the intended hardening improvements would be entirely impossible. BENEFIT: Higher density memory with significantly improved power and reliability with high radiation tolerance. Also due to the sharing of volume commercial pieces, a more reasonable cost structure should be achievable.