SBIR/STTR Research Award

Low-Power, Rad-hard Reconfigurable, Bi-directional Flexfet¿ Level Shifter ReBiLS for Multiple Generation Technology Integration for Space Exploration

Award identifier 77f4f0a95037708b92dbe14e461cceaa670c4c862a8bf67ca4c06ae83afa6bbcAwarding agency National Aeronautics and Space Administration

Award amount

$599,909

Program and phase

SBIR · Phase II

Award year

2006

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Award details

Awarding agency
National Aeronautics and Space Administration
Branch
Not reported
Recipient company
AMERICAN SEMICONDUCTOR, INC
Proposal award date
2005-12-20
Contract end date
2007-12-19
UEI
C1BNR9HJBQK8
Solicitation number
Not reported
Topic code
S1.04

Research abstract

The many different generations of integrated circuit (IC) technologies required for new space exploration systems demand designs operate at multiple and often incompatible voltages. Extended utilization of current and development of new space exploration systems require multiple voltage levels be successfully integrated to interface technologies. NASA's micro-satellites and space exploration missions, like the Space Technology 5 (ST5) Project, are current examples of systems that employ a variety of voltage levels. Spacecraft have limited supply voltages and power at their disposal and this encourages the use of a higher percentage of low voltage microelectronics. [4] To build complete systems there continues to be a common problem of mixing old and new equipment operating at different voltages. [3] ASI's FlexfetTM CMOS rad-hard reconfigurable bi-directional level shifters (ReBiLS) will allow NASA improved capability to design, develop and implement multi-level voltage systems. The ASI ReBiLS Phase II project will generate prototypes for stand-alone and embedded bidirectional level shifters. A stand-alone ReBiLS device will allow designers to provide efficient bi-directional communication between existing or COTS components operating at different voltages. An embedded ReBiLS cell will be demonstrated in a CULPRiT ULP circuit to demonstrate the on-chip integration of low-voltage, low-power core logic with high-voltage I/O.

Technology keywords

Not reported

Other awards by this recipient

Verified by the same UEI. These are other public SBIR/STTR award pages, not a merged company record.

Awards with the same topic code

Verified by an exact topic code match. This is not a text-similarity match.

Research funding history

22 SBIR/STTR records share this UEI (2002–2025). Reported award amounts total $8,230,994. Reported amounts are not federal obligations.

Phases: Phase I, Phase II

Agencies: Department of Defense, Department of Energy, National Aeronautics and Space Administration

Agency intelligence

National Aeronautics and Space Administration

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