Alternate Architecture For Focal Plane Resistive Grid Processing and Readout

Low power real-time processing of large area image sensor data is not computationally feasible using existing digital technology. This computational bottleneck is circumvented by using neuromorphic arrays in low-power analog vision processing systems.Computational Sensors Corporation (CSC) proposes to develop core enabling technologies that comprise a new massively parallel 3-D structure of highly integrated, multi-layered, programmable analog VLSI image processing architecture to meet navigation and guidance requirements in mobile platform applications, enabling the first new architectural approach to the readout of staring focal plane sensors since their invention in the early 1970's - continuous parallel processing without synchronous multiplexer operations.We propose to develop modular, wide dynamic range analog filter array layers for incorporation into multi-layered architectures using state-of-the-art micro-via vertical interconnect technology to seamlessly link unit cells of adjacent layers. This concept extends our previous work using Thin Film Analog Image Processors (TAIP) and CMOS analog image processors for spatio-temporal motion detection. The new architecture will provide continuous, non-multiplexed, computational capabilities that allow direct (no storage well) sampling of IR sensor irradiance. Full utilization of the sensor spectral dynamic range, improved signal to noise performance, and alias free operation will be possible as in biological systems.