Cryogenic Radiation-Hard Read-out Integrated Circuit Electronics Process Design Kit

The objective of this Phase I SBIR proposal is to develop a process design kit (PDK) for use in the design of radiation-hardened integrated circuits operable at cryogenic temperatures, down to 45 K, such as read-out integrated circuits (ROIC) for infrared detector arrays. Apogee Semiconductor is a developer and provider of rad-hard PDKs for use in the IC foundry and fabless IC industry, for the design of CMOS and BiCMOS ICs used in defense electronics, medical imaging, and other high-radiation environments. In this Phase I project, Apogee will design test chips with the use of Apogee’s patented rad-hard transistor-level technology, which typically provides a ~10x improvement in TID radiation hardness. The test chips will include varying design parameter spacings for transistors to characterize total ionizing dose and single event effects from 45K to room temperature. Test chip designs and a design-of-experiments matrix specifying design rules will be delivered at the end of Phase I. Apogee Semiconductor has partnered with a state-of-the-art foundry to implement the PDK technology proposed for this SBIR project on a 90nm CMOS node. The rad-hard cryo-temp PDK developed under this project will be made available to all domestic developers in the space electronics community upon completion.